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ten. The apparatus for detecting clock tampering as described in assert eight, wherein the signifies for triggering the implies for assessing works by using a clock edge at an end of the clock Appraise period of time to bring about the means for analyzing.
In other extra comprehensive facets of the invention, Just about every of the plurality of delayed monotone indicators 230 might be either a 1 or possibly a zero. The Assess circuit 240 may possibly decide no matter whether the number of ones within the plurality of delayed monotone alerts differs from the h2o amount variety by much more than a predetermined threshold.
The steps of a way or algorithm explained in connection with the embodiments disclosed herein might be embodied straight in hardware, or in a mix of components and also a software module executed by a processor. A software module may possibly reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, really hard disk, a detachable disk, a CD-ROM, or some other type of storage medium known within the artwork.
an Examine circuit, activated by the clock, that employs the plurality of delayed monotone alerts to detect a clock fault.
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Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are offered. Resettable delay line segments in between a resettable hold off line phase connected with a least delay time as well as a resettable delay line segment connected with a greatest delay time are Every related to discretely growing hold off times.
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